Cadence has taken a groundbreaking step in pre-silicon power analysis by joining forces with NVIDIA. Through this strategic collaboration, Cadence leveraged the advanced Cadence Palladium Z3 Enterprise Emulation Platform and its newly launched Dynamic Power Analysis (DPA) App to achieve what was once deemed impossible hardware-accelerated dynamic power analysis for billion-gate AI designs, spanning billions of cycles within just a few hours and delivering up to 97% accuracy.
This remarkable achievement marks a game-changer for semiconductor and systems developers working on AI, machine learning (ML), and GPU-accelerated applications. By enabling energy-efficient system design and faster time-to-market, the innovation empowers engineers to meet aggressive power and performance targets without compromising accuracy.
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Traditionally, predicting power consumption under realistic workloads for today’s most advanced chips has been a major bottleneck. Standard power analysis tools often stall after a few hundred thousand cycles, requiring impractically long timelines. However, Cadence and NVIDIA broke through these limitations by combining hardware-assisted power acceleration with parallel processing innovations, delivering unmatched precision across billions of cycles in early design stages.
Dhiraj Goswami, Corporate Vice President and General Manager at Cadence, highlighted the transformative nature of the achievement: “This project redefined boundaries, processing billions of cycles in as few as two to three hours. It enables customers to meet performance and power goals with confidence and bring their designs to silicon faster.”
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Narendra Konda, Vice President of Hardware Engineering at NVIDIA, emphasized the growing need for such capabilities: “As the era of agentic AI and next-generation AI infrastructure evolves, engineers require advanced tools for energy-efficient designs. By combining NVIDIA’s accelerated computing expertise with Cadence’s EDA leadership, we’re delivering more precise efficiency in accelerated computing platforms.”
With the Palladium Z3 platform powered by the DPA App, designers can accurately estimate power consumption under real-world workloads before tapeout allowing for optimization at the most critical stage. Particularly for AI, ML, and GPU-driven applications, this early modeling significantly boosts energy efficiency while avoiding delays caused by over- or under-engineered chips.
By integrating Palladium DPA into its full analysis and implementation suite, Cadence ensures that power estimation, reduction, and signoff are addressed throughout the design cycle resulting in the most efficient silicon and system designs possible.
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